The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 31, 1984
Filed:
Feb. 08, 1982
Veikko R Saari, Spring Lake Heights, NJ (US);
Bell Telephone Laboratories, Incorporated, Murray Hill, NJ (US);
Abstract
A high performance operational amplifier 12 circuit 10 nulls the offset voltage by means of switched capacitors (C.sub.2, C.sub.3) and holds the signal output 18 during the nulling. Switching is in response to two non-overlapping pulse trains .phi..sub.1, .phi..sub.2. During an output valid phase .phi..sub.1, with the signal input source connected to the inverting input 14 of the amplifier 12, an offset voltage storage capacitor C.sub.2 is connected between the non-inverting input 16 and ground. A signal storage capacitor C.sub.3 is connected between the output 18 and ground. During a nulling phase .phi..sub.2, the signal storage capacitor C.sub.3 is disconnected from ground and connected between the output 18 and the inverting input 14. The previously grounded side of the offset voltage storage capacitor C.sub.2 is switched to the inverting input port 14. The non-inverting input port 16 is grounded. The offset storage capacitor C.sub.2 charges to the input offset voltage, while the inverting input 14 is reset to virtual ground. When the circuit 10 is reconnected in the .phi..sub.1 valid output phase, the offset is compensated by the input offset storage capacitor C.sub.2 without the output 18 having been directly connected to the inverting input 14. This makes possible a shorter settling time. Also disclosed as optional is an output offset limiting feedback network 35 for preventing a locking of the circuit 10 which can result from excessive initial offset voltage and a capacitor C.sub.4 connected between the input side of the signal hold capacitor C.sub.3 and the inverting input 14 to prevent sensitivity to clock leakage.
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