Buffer circuit and integrated semiconductor circuit structure formed of

Abstract

A monolithic integrated circuit structure consisting of interconnected bipolar and CMOS transistor elements forming a buffer circuit. A pair of NPN bipolar transistor elements are interconnected with a pair of N-type MOS transistor elements to form a push-pull output stage providing complementary outputs at the emitters of the bipolar transistor elements. Each of the pair of NPN bipolar transistor elements is arranged in an emitter follower circuit configuration having the conducting channel of one of the pair of N-type MOS transistor elements serially connected to its emitter. The gate electrode of each of the pair of MOS transistor elements respectively is connected to the emitter of the bipolar transistor element to which the conducting channel of the other of the pair of MOS transistor elements is connected. P-type and N-type MOS transistor elements are serially interconnected in a complementary symmetry manner to form an inverter circuit configuration. The complementary interconnected MOS transistor elements have their drains connected together to the base of one of the pair of bipolar transistor elements and their gate electrodes connected together to the base of the other of the pair of bipolar transistor elements, the connected gate electrodes and base forming the buffer circuit input. The collectors of the bipolar transistor elements and the source of the P-type MOS transistor element are connected together to define a positive supply voltage terminal and the sources of the N-type MOS transistor elements are connected together to define a reference potential terminal.