Phase sensitive detector

Abstract

As shown in FIG. 7, a phase sensitive detector comprises two D-type flip-flops 701 and 702 which are arranged so that in response to data pulses DP and clock pulses CK they produce respective pulse sequences D1 and D2. FIG. 8 shows the relative timing of these pulses and pulse sequences. An exclusive OR-gate 703 receives the pulse sequences D1 and D2, and an exclusive OR-gate 704 receives the pulse sequence D1 and the data pulses DP. The clock pulses CK can be up to one half a clock pulse period late or up to one half a clock pulse period early relative to a desired phase relationship of the clock pulses CK with the data pulses DP. According as the actual relative phase is correct, late or early, the duration of the logic output from the gate 704 will be the same as, proportionately longer than, or proportionately shorter than, the duration of the logic output from the gate 703. The two gate outputs control respective current sources 707 and 708 of a current source circuit 705 to drive current into and extract current from a capacitor 203. The voltage across the capacitor 203 serves as a control voltage for altering the phase of the clock pulses CK, as produced by some form of oscillator, to tend to bring it into the desired phase relationship with the data pulses DP.