Sense amplification scheme for random access memory

Abstract

In source-clocked type of cross-coupled latch sense amplifier of a dynamic random access memory device, there is provided a sense clock that employs multiple extended dummy memory cells to provide reference timing which tracks time constants of word line, cell transfer gate, cell capacitor, and bit line, and the sense clock is further compensated over large variations of fabrication process parameters and operating conditions. The trigger and slave clock circuit are chained in series to control the timing sequence of a plurality of clocked output signals. The clocked output signals are selectively amplified and summed in parallel to generate current with an intended dynamic characteristic. The current so generated is applied to the common source electrodes of the cross-coupled latch.