The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 22, 1983

Filed:

May. 05, 1980
Applicant:
Inventor:

Leonard F Shepard, Lake Grove, NY (US);

Assignee:

ILC Data Device Corporation, Bohemia, NY (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K / ; H03K / ; H03K / ; H03H / ;
U.S. Cl.
CPC ...
377 43 ; 328 55 ; 328154 ; 328155 ; 377 47 ; 377 52 ;
Abstract

Apparatus for imparting a delay to an input signal utilizing counter means comprised of a plurality of binary coded decimal counter stages connected in cascade. The high frequency input signal applied to the counter undergoes a divide-by 10.sup.N operation wherein N equals the number of binary coded decimal stages. Preferably, the least significant stage is adapted to be selectively and periodically preset to a binary coded decimal value different from its normal reset state to either increase or reduce the number of pulses required to cause the counter stage to read a terminal count to selectively either advance or retard the phase of the reduced frequency output signal developed at the output of the counter relative to the phase of the input signal applied to the counter in accordance with a preprogrammed value set into said counter stage. The number of advance or retard phase offsets may be adjusted over a wide range through the employment of a rate multiplier which sets the aforementioned presettable decade stage a predetermined number of times over a given time interval. The rate at which the said presettable decade stage is set is controlled by an adjustable rate generator which drives the rate multiplier. The number of times which the digital time incrementer is preset over the aforesaid interval is controlled by the setting of the adjustable rate multiplier. Input means are provided for substituting one high frequency input source for another without imposing any additional delay in the signal undergoing a phase adjustment due to the substitution. The digital time incrementer is advantageously incorporated into a microphase stepper capable of providing extremely small precision changes in phase as between an input and an output frequency wherein the output frequency is either equal to or a multiple or submultiple of the input frequency.


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