Programmable sequential logic circuit devices

Abstract

The programmable sequential logic circuit device is constructed to sequentially form an output signal to an external circuit and the circuit state for the next operation in accordance with input signals applied from outside and the internal state of the circuit. The device includes a first logic array for producing product terms of the input signals, a second logic array for producing sum terms of the first logic array, a two-dimensionally arrayed flip-flop array and means for setting the state of the flip-flop array. The flip-flop array is arranged in a plurality of rows of stages each including a plurality of serially connected flip-flop circuits. The inputs of respective rows are connected to the outputs of the second logic array, the outputs of the setting means are applied to the inputs of respective stages and the outputs thereof are parallelly fed back to the first logic array.