The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 01, 1983
Filed:
Feb. 22, 1982
Kazuyoshi Shinada, Yokohama, JP;
Tokyo Shibaura Denki Kabushiki Kaisha, Kawasaki, JP;
Abstract
Disclosed is a method for manufacturing a semiconductor device. In this method an oxidation-resistive insulating film is formed on a silicon body of a one conductivity type. A first impurity region of the opposite conductivity type is selectively formed in said semiconductor body before or after said insulating film is formed. Part of said insulating film which corresponds to part of said first impurity region is etched and exposed portions of said silicon body are etched by isotropic etching to a predetermined depth, using said oxidation-resistive insulating film as a mask. An impurity of the opposite conductivity type is doped into said first impurity region, using said insulating film as a mask, so that a second impurity region of the opposite conductivity type whose concentration is higher than a concentration of said first impurity region is formed in said first impurity region and said silicon body. Thermal oxidation is performed using said insulating film as a mask, so that a continuous oxide film is formed to cover exposed portions of said first impurity region, said second impurity region and said semiconductor body. And a third impurity region of the one conductivity type is formed in said first impurity region which is exposed, after part of said insulating film on said first impurity region is etched. The method of this invention is advantageous for manufacture of a bipolar integrated circuit of high switching operation, high integration density and high reliability.