Three state loop keyer

Abstract

A transistorized keying circuit is described which provides for both polar and neutral interfacing. The circuit comprises an oscillator, an AND gate, an exclusive OR gate, a transformer, and two similar output circuits each of which is connected to the secondary of the transformer. The oscillator produces a high frequency binary output signal having an asymmetric duty cycle. The output of the oscillator and a low frequency data signal are applied to the AND gate. The output of the AND gate and another low frequency data signal are applied to the exclusive OR gate whose output is amplified and applied to the primary of the transformer. Each output circuit coupled to the secondary of the transformer comprises a switching transistor for switching a supply voltage onto a transmission line and a peak detector for controlling the operation of the switching transistor. When the AND gate is enabled and the output signal from the exclusive OR gate is the oscillator output signal, only one of these transistors is switched ON; and when the output of the oscillator gate is the inverted signal only the other transistor is switched ON. When the AND gate is disabled, neither transistor is switched on. For polar operation of this circuit, the opposite end of the transmission line is connected through a load resistor to voltage supply common. For neutral operation either the AND gate can be enabled and disabled or the load resistor can be connected to voltage supply positive or negative.