The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 18, 1983

Filed:

Feb. 17, 1981
Applicant:
Inventors:

Edward P Daniels, Bridgeport, CT (US);

Daniel F Dlugos, Huntington, CT (US);

Earl B Holtz, Huntington, CT (US);

Flavio M Manduley, Woodbury, CT (US);

Assignee:

Pitney Bowes Inc., Stamford, CT (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F / ; G01G / ;
U.S. Cl.
CPC ...
364900 ; 364466 ; 177 25 ;
Abstract

An automated mailing system includes a postage value determining system processor, a scale for providing weight indicative signals, a keyboard for operator entry of information relating to a determination of postage, and a plurality of peripheral devices. A peripheral controller interface establishes communications links with the peripheral devices. An incompatible systems interface interconnects a serial communications bus of the system processor and the peripheral controller interface. The incompatible systems interface includes a processor programmed to receive, decode and transmit information from or to the system processor along the serial bus and load or receive information from or to the peripheral controller interface along parallel lines. The communication timing constraints of the serial communications bus for receipt of data signals by the system processor do not permit monitoring of the data transmission by the incompatible systems processor. To accommodate for such timing constraints, system clock pulses of the serial bus are employed at a flip-flop to disable the incompatible systems processor.


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