The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 18, 1983

Filed:

Dec. 29, 1980
Applicant:
Inventors:

Arthur B Barrow, Acton, MA (US);

Horace H Tsiang, North Andover, MA (US);

Assignee:

Wang Laboratories, Inc., Lowell, MA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F / ;
U.S. Cl.
CPC ...
364200 ;
Abstract

A multitasking data processing machine supports virtual memory comprising a plurality of segments, and has physical memory comprising relatively fast main memory and relatively slow secondary memory. A constantly varying subset of secondary memory paged contents is copied in main memory page frames. When a memory access is required during operation of the machine, a virtual address is generated, which must be translated into a physical address, in order to address main memory. The data processing machine provides an indexed local random access memory (T/RAM) for storing previously translated addresses. The T/RAM has a capacity of one entry for each page of supported virtual memory. Before a translation is performed, the T/RAM is indexed by the virtual address; in case of a T/RAM fault, translation is performed and the translated physical address is loaded to the indexed location before restarting the memory operation. A subsequent reference to the same virtual address indexes the previously translated physical address, which is then used for addressing main memory and is also applied to index a reference/change table. A stored monitor/no monitor signal associated with each segment of virtual memory controls the storage of referenced virtual addresses for monitored segments. Upon a task switch, the stored virtual addresses are applied to index the corresponding T/RAM entries for rapid selective and partial clearing of the T/RAM.


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