Data processor adapted for interruption to an instruction stream

Abstract

An information processing system having an instruction unit for decoding each of successive instructions to generate an address of a next instruction, and additionally, when a branch instruction is decoded, a branch-to address of the decoded branch instruction. An execution unit sequentially executes the decoded instructions and a plurality of registers are provided for storing the next instruction address and the branch-to address. A pointer is generated to indicate one of the registers in which the next instruction address or the branch-to address is to be stored and the pointer is changed sequentially and cyclically in response to a first signal which is generated by the execution unit upon completion of execution of each decoded instruction or a second signal which is generated by the execution unit upon success in branch when a branch instruction is executed. Further provided is a delay circuit for receiving the pointer and generating it at a predetermined time delay. The delayed pointer is latched at a timing predetermined by the first and second signals and an interrupt signal produced, upon detection of an interrupt request, at a timing determined in dependence on the type of the interrupt request, and the instruction address used for a program status word is read out of one of the registers indicted by the latched pointer.