The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 11, 1983

Filed:

Mar. 03, 1982
Applicant:
Inventors:

Takashi Nakamura, Atsugi, JP;

Yoshihiro Morioka, Atsugi, JP;

Kazunori Yamaji, Atsugi, JP;

Takashi Nakamura, Atsugi, JP;

Yoshihiro Morioka, Atsugi, JP;

Kazunori Yamaji, Atsugi, JP;

Assignee:

Other;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H04N / ;
U.S. Cl.
CPC ...
358 51 ;
Abstract

Deflection control apparatus for registering the electron beam, rasters of electrostatic-deflection pick-up tubes of a three-tube color television camera includes a compensating voltage generator with inputs connected to receive horizontal and vertical sawtooth deflection signals provided from a deflection signal generator, and outputs providing compensating voltages to adjust for size, skew, and rotation. A combining circuit is provided to add the deflecting signals to the respective compensating voltages to generate adjusted compensating voltages for application to respective electrostatic deflection plates of certain ones of the tubes. For each adjusted deflecting signal, the combining circuit includes a transistor circuit having an input electrode coupled to receive the associated compensating voltage and an output electrode connected through a load resistor to an output of the deflecting signal generator. A pair of SEPP-arranged transistors are provided with their bases connected to the output electrode of the transistor circuit and with their emitters coupled together, through like-value emitter resistors, to a respective deflection plate of one of the tubes. The SEPP-configured transistors permit a high impedance to be presented to the deflection signal generator to minimize the power consumption thereof, and a low resistance to be presented to the deflection plates, to keep the latter from undesirably integrating the deflection sawtooth voltages.


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Nakamura, Takashi. (1983). Sepp-based deflection control circuit (U.S. Patent No. 4409613). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/4409613

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