The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 30, 1983
Filed:
Oct. 19, 1981
Anthony D Newton, Geneva, CH;
Motorola, Inc., Schaumburg, IL (US);
Abstract
A TV timebase circuit includes a vertical sync counter in the form of a ten-bit ripple-through counter. Additional logic circuitry including a pair of divide-by-four counters, a latch, a D flip-flop, and associated AND, NAND, and invertor gates are also provided. The circuit is responsive to a multiple of the horizontal frequency and to vertical sync pulses and is capable of automatic recognition of 525 or 625 line standard. The logic includes a mechanism for locking out the vertical counter's 525 count when operating in the 625 mode. The latch, in association with one of the divide-by-four counters serves a 'fly wheel' sync function, whereby a predetermined number of 'matches' must be recognized to lock the circuit into a given mode, and whereby a predetermined number of 'mis-matches' must occur to drop the circuit operation from the locked-in mode. Several outputs are taken off the vertical counter to operate ramp drive and blanking functions of the TV vertical sweep generator. An output representative of the particular line standard being decoded may be used to provide chrominance decoding information and picture height control information. An alternative embodiment capable of recognizing any given TV line standard comprises a register which is loadable with the line standard number, which in turn is provided from the vertical counter cumulative count between successive vertical sync pulses, the vertical counter being reset by each vertical sync pulse. Comparison logic is provided for locking the counter circuit onto a given line standard after a predetermined number of successful matches have occurred between the contents of the register and the vertical counter count at the moment of reset by the vertical sync pulse.