The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 16, 1983
Filed:
Dec. 30, 1980
Kazunari Shirai, Yokohama, JP;
Fujitsu Limited, Kanagawa, JP;
Abstract
A plural layered wiring which comprises a plurality of polycrystal semiconductor layers can be improved in its magnitude of circuit integration, when one or more upper polycrystal semiconductor layers which is or are doped to a moderate impurity concentration is or are utilized as resistor elements, the lowest polycrystal semiconductor layer which is highly doped is utilized for electrodes and/or wirings for active elements, and both polycrystal layers are connected with each other by regions which are highly doped by upward diffusion of impurities contained in highly doped regions of a substrate, because this configuration entirely avoids the restriction that is imposed for the location of resistor elements arranged in the upper layers. This arrangement is realized by a specific sequential combination of steps which includes a step of upward diffusion of impurities from the highly doped regions of the substrate. An additional advantage of this method is the exclusion of a so-called non-butting process.