The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 02, 1983
Filed:
Oct. 01, 1973
Ingrid E Magdo, Hopewell Junction, NY (US);
Steven Magdo, Hopewell Junction, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A dielectrically isolated semiconductor device can be manufactured. The structure is useable for integrated circuits, including field effect and/or bipolar transistors, wherein a significant savings in surface area and reduction in capacitances can be obtained over prior techniques. The method involves forming a layer of dielectric material upon a semiconductor body, having a diffused region where a bipolar device is to be formed, and then forming an opening in the layer to expose a part of the surface of the diffused region of the semiconductor body. An epitaxial layer of silicon is deposited on top. Single crystal silicon will grow over the exposed silicon area and if a diffused region is present in the substrate a pedestal will outdiffuse through the same area from the buried diffused region. Polycrystalline silicon will grow on top of the dielectric material. The pedestal is formed in a single crystal epitaxial layer of another impurity type. Two other active elements of a bipolar transistor, such as the emitter and intrinsic base regions, are then formed in the same single crystal epitaxial layer while the inactive area, such as the extrinsic base, is formed in polycrystalline silicon. A reach through is made through the dielectric layer to the third element of the transistor, that is collector region.