Interconnect fault detector for lsi logic chips

Abstract

A large-scale integrated circuit (LSI) chip has an individual voltage level sensing circuit connected with each input and output connecting pin so that isolation between the pins is maintained and so that the individual level sensor output can provide an indication of an abnormal voltage on the input/output pin. The outputs of all level sensors for all input and output pins is connected in common to the input of a comparator circuit. The comparator circuit has a fault detection threshold voltage input and provides a fault indication output signal whenever the voltage input from the level sensor circuits is outside of the detection threshold voltage range. A number of logic chips will have particular input/output pins connected together in a circuit in conventional applications. An open circuit anywhere in the interconnected network will cause some number of input/output pins dependent on the fault location to be pulled out of the detection threshold voltage range. Similarly, any short circuit to ground condition will also cause a voltage shift outside of the detection threshold voltage range. Further, interconnect faults which result in impedance mismatch and cause a 'ringing' signal voltage outside of the threshold detection voltage range, will also be detected as a fault signal. Thus, the fault detection system of the present disclosure will detect a number of types of faults in interconnection networks of various logic chips.