Memory addressing circuit for converting sequential input data to

Abstract

A system for converting sequentially received data words, in the form of successively received groups of data words, into an interleaved output data word sequence, with each group of received data words consisting of T successive series of R data words. The system comprises N memories, each having W words locations, where W.multidot.N.gtoreq.T.multidot.R and where the N memories form a single memory matrix which is employed to process every group of received data words. Writing logic is provided for writing successively received data words of a first group of data words into the N memories in a predetermined sequence. Reading logic is provided for reading from the memories every R.sup.th data word of the first group of data words written into the to leave an available word location in each instance where a data word was read therefrom. The writing logic also includes logic for writing successively received data words of each subsequently received group of data words into successively occurring available word locations created by the reading therefrom of the data words of the immediately preceding group of data words.