The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 05, 1983

Filed:

Dec. 24, 1980
Applicant:
Inventors:

Takaaki Yamada, Kanagawa, JP;

Yoshio Osakabe, Kanagawa, JP;

Yukio Tsuda, Kanagawa, JP;

Assignee:

Sony Corporation, Tokyo, JP;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H04B / ; H03J / ; H03L / ;
U.S. Cl.
CPC ...
455165 ; 331 / ; 455183 ;
Abstract

A frequency synthesized receiver utilizes, as a local oscillator, a phase-locked circuit formed of a reference signal oscillator, a voltage controlled oscillator, a programmable divider, a phase comparator, and a low-pass filter. For tuning to a desired frequency, the dividing ratio of the programmable divider is controlled by an up/down counter connected in parallel with a shift register. The latter is supplied with a clock pulse signal and a binary coded selecting signal furnished from a micro computer. The selecting signal corresponds to a desired broadcast frequency. The up/down counter is caused by the micro computer to count up or down from the count value stored in the shift register, thereby causing the received frequency to rapidly sweep, at predetermined steps of, for example, 100 KHz.


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Yamada, Takaaki. (1983). Phase locked loop circuit (U.S. Patent No. 4392253). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/4392253

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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