Multi-bit read only memory circuit

Abstract

A ROM circuit (10) includes a plurality of multi-bit memory storage transistors (22, 24, 26, 28, 29) and reference transistors (40, 42 and 44) all connected along a word line (16). Each of the storage transistors is provided with bit (18) and column (20) lines for activating a specific memory storage transistor and transmitting the data state thereof to sensing circuitry. A step control signal is transmitted through a control line (80) and applied to a selected one of the memory storage transistors and to each of the reference transistors (40, 42 and 44) on a selected word line (16). The step control signal is sequentially decreased in voltage to apply a progressively increasing gate-to-source voltage to each of the reference transistors (40, 42 and 44) and to a selected one of the memory storage transistors (26). The reference transistors (40, 42, and 44) are sequentially turned on by the increasing gate-to-source bias generated by the step control signal. The steps of the step control signal are generated in response to the turn on of the reference transistors (40, 42 and 44). The selected memory storage transistor (26) is turned on when the gate-to-source voltage of the transistor (26) is reached. At the time that the memory storage transistor (26) is turned on the condition of the reference transistors (40, 42 and 44) is latched to determine the voltage threshold level of the selected memory storage transistor (26). The latched conditions of the reference transistors (40, 42 and 44) are then decoded to produce the appropriate output signals corresponding to the data state fabricated into the selected memory storage transistor (26).