Central processor with apparatus for extended virtual addressing

Abstract

A central processor for use in a data processing system that is adapted for addressing a substantially larger virtual memory than the address space defined by the memory address field in an instruction normally provides. Information identifying an extended address is placed in working registers of the central processor. Other working registers in the central processor receive information corresponding to the memory word addressed by the instruction word. If the memory word requires indexing, the central processor adds the contents of an index register to the address contained in the memory address field of the memory word. If the resultant address is extended, the arithmetic and logic unit's carry logic is not inhibited and the larger address space is provided to one of the working registers. Concurrently, control logic is set within the central processor which causes the central processor to interpret the information as an extended address. If the memory word indicates that another memory word is required, the central processor performs similar calculations on the indirect word until an effective address is calculated. Several levels of indirection can be performed depending upon the characteristics of each preceding indirect word.