Pseudo-random noise generated target simulator

Abstract

A target simulator tests the characteristics of a multi-element array witt the use of large memories and long delay line storage. The simulator includes a master clock which provides the count frequency to a binary counter. The reading of the binary counter is compared in a comparator with a stored number in a sequence from a programmable readable memory (PROM). On agreement the comparator feeds an output to an appropriate member of a group of hydrophone counters. Upon receipt of the signal from the comparator the counter provides a signal to the PROM. The PROM then provides its next synchronizing binary number to the comparator. The hydrophone counter also provides a signal to the channel selector reset which resets an appropriate pseudo-random noise generator (PRNG) to produce an output of the target simulator.