The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 24, 1983
Filed:
Sep. 25, 1980
Thomas S Spinelli, Attleboro, MA (US);
William G Manns, Dallas, TX (US);
Donald F Weirauch, Dallas, TX (US);
Texas Instruments Incorporated, Dallas, TX (US);
Abstract
An electronic circuit interconnection system permitting high density mounting of ceramic chip-carrier integrated circuit devices or other beam-lead, dual-in-line (DIP), tape-automated-bonded (TAB), flip-chip, or direct-mounted i.c. devices with wire-bonded interconnects or the like has economical, dimensionally-stable, interconnection substrate which has high heat dissipating properties. The substrate has glass components which are fused onto etched metal patterns and which are proportioned relative to the metal patterns so that the heat-expansion properties of the substrate correspond to those of the i.c. devices to maintain bond integrity between the i.c. leads and circuit paths on the substrate and so that the substrate has sufficient heat-dissipating properties to permit the high density i.c. mounting. The substrates incorporate circuit paths, device mounting pads, edge terminals, pin mounting holes and other typical substrate features in the etched patterns in multimetal laminated metal plates of selected thickness which are coated on one or both sides with glass frit fused to the plates. Where substrates with more than one layer are desired, glass-coated plates are stacked with pin mounting holes and the like aligned and the glass coatings are fused together. Metal vias extend through the glass coatings where desired to interconnect metal layers of the substrate.