Combined use of pn sequence for data scrambling and frame

Abstract

In a communication system containing a scheme for externally synchronizing and scrambling digital data signals, serial digital data signals to be transmitted are subdivided into prescribed numbers or sets between which additional or overhead bits are inserted, the resulting sequence being summed in a modulo-two adder with a multi-bit maximal length PN sequence, so that one of the overhead bits is one of the bits of the maximal length scrambling sequence. A multiplexing operation yields a higher data rate sequence which is then modulo-two added with the output of a scrambler and transmitted. At the receiver station, the incoming scrambled sequence is applied to timing recovery circuitry including a local framing sequence generator. The framing sequence is located and the stages of a separate shift register, which forms part of a descrambler PN sequence generator, are forced to a state which is coincident with the frame marker. This shift register is clocked at the incoming data rate by the recovered clock from a timing recovery circuitry and its output is modulo-two added with the incoming digital data stream, thereby recovering the original multiplexed data. In order to recover the original data, the descrambled sequence is applied to a demultiplexer which effectively deletes every overhead bit and outputs the original data at the original data rate.