Transistor-transistor logic input buffer circuit with power

Abstract

An MOS input buffer circuit for receiving transistor transistor logic (T.sup.2 L) logic level input signal includes a plurality of inverting amplifier stages. The input signal is applied to the gate electrode of a first field effect transistor in the first inverter stage and may assume a high logic level of as low as 2 volts and a low logic level of as high as 0.8 volts. In order to provide a stable switching point at the output of the first inverter stage, a feedback field effect transistor is coupled between the output of the first inverter stage and ground and has its gate electrodes coupled to a source of supply voltage (V.sub.DD). As V.sub.DD increases, the feedback field effect transistor will sink more current and thus alter the gain of the first amplifying stage to stabilize its switch point. To further enhance the tracking capabilities over temperature and process variations, the first two inverter stages are comprised entirely of field effect transistors of the enhancement type and having substantially equal channel lengths.