Process of performing burn-in and parallel functional testing of

Abstract

A process performed by the manufacturer for testing integrated circuits (ICs) to insure better quality and higher reliability thereof and to eliminate the need for incoming inspection and board level testing by the chip customer. In the embodiment disclosed, in-process testing, wafer-probe testing, die separation, packaging, and one by one assembly line testing of the digital memory ICs for catastrophic failures all proceed according to conventional techniques. A large number of the ICs are then plugged into high-temperature, high signal integrity PC storage cards, each adapted for interconnecting the ICs in row-column arrays to form a memory board. The storage cards are mounted within an environmental chamber and are operatively coupled to corresponding PC driver cards mounted externally of the chamber. Next, accelerated dynamic burn-in of the ICs takes place. The PC storage cards are constructed to electrically isolate groups of the ICs so that if an IC in one group has a shorted input, the ICs in the remaining groups will still receive the appropriate dynamic signals to ensure burn-in thereof. Thereafter long functional/pattern testing of the ICs with continuous error logging occurs while the ICs are still mounted in the chamber. Finally the PC storage cards are removed from the chamber and those ICs which have logged either hard or soft errors are separated. The remaining good ICs are subjected to one by one short functional testing to determine compliance with data sheet specs. After quality control testing, the good ICs are shipped to the chip customer who can safely assemble them into user systems without performing the usual customer level incoming inspection and board level testing.