Latching pulse width modulation comparator

Abstract

A pulse width modulation comparator having internal latching and resetting functions. The comparator includes a differential input stage having first and second outputs which are connected to supply first and second transistors in a voltage gain stage, respectively. The first output of the input stage drives both of the transistors of the voltage gain stage. The second output of the input stage is connected to drive an output transistor as well as to supply the second transistor of the voltage gain stage. The output of the output transistor is connected via feedback circuitry to drive the transistors of the voltage gain stage. A shunt transistor forms part of the feedback circuit and serves to divert the feedback signal from the voltage gain stage transistors upon the application of a clock reset pulse. An analog voltage is applied to one input of the input stage and a ramp or triangular waveform is applied to the other input. At the point where the ramp exceeds the analog voltage, the voltage gain transistors are turned on and the second output of the input stage goes low, aided by the voltage gain stage. This causes the output transistor to go high, thereby generating positive feedback to drive the voltage gain transistors, thereby latching the output transistor in a high state. At the end of the ramp period, a clock pulse turns on the shunt transistor so as to remove the feedback current from the voltage gain stage and reset the output transistor to a low level.