The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 22, 1983
Filed:
Feb. 12, 1980
Applicant:
Inventors:
Assignee:
Mitsubishi Denki Kabushiki Kaisha, Tokyo, JP;
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L / ; H01L / ;
U.S. Cl.
CPC ...
3072 / ; 3072 / ; 307304 ; 357 48 ; 357 51 ; 357 23 ;
Abstract
An insulated gate field-effect transistor (MOS.multidot.FET) formed as a basic element of an integrated circuit formed together with a substrate bias circuit in a semiconductor substrate having negative potential. In the substrate bias circuit, semiconductor regions (p.sup.+ -regions) having impurity concentrations higher than that of the semiconductor substrate (p-type) are formed between the semiconductor regions (n.sup.+ -region) and the semiconductor substrate (p-type) to form n.sup.+ p.sup.+ p-diodes.
Yoshihara, Tsutomu. (1983). Substrate bias circuit (U.S. Patent No. 4377756). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/4377756
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile