The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 01, 1983

Filed:

May. 21, 1981
Applicant:
Inventor:

Man S Lee, San Mateo, CA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03H / ;
U.S. Cl.
CPC ...
333213 ; 328128 ; 328167 ; 330107 ; 333217 ;
Abstract

An integratable circuit that simulates a source resistor comprises first and second nodes for connection to a voltage source and a virtual ground, respectively; a first integrated capacitor C1; and switch means operative for alternately electrically connecting C1's top and bottom plates to the first node and ground, respectively, and to ground and the second node, respectively, during first and second non-overlapping time periods in each time interval T for charging C1 to the source voltage and discharging C1 into the second node, respectively, where T is the time interval between adjacent second time periods and f=1/T is the switching frequency for C1. The switch means also operates for making similar connections to plates of second and third capacitors C2 and C3 in different time periods of ones of successive time intervals T, both C2 and C3 sampling a source voltage in synchronism with sampling by C1 during adjacent time intervals and holding a charge voltage for a time interval T prior to being discharged into the second node. The circuit simulates a source resistor when the first node is electrically connected to the output terminal of a voltage source that is connected to ground. This circuit configuration simulates a bilinear source resistor when the capacitances are the same values and the circuit is characterized by the bilinear transformation.


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