The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 08, 1983

Filed:

Feb. 06, 1981
Applicant:
Inventors:

Theodore A Fulton, Warren Township, Somerset County, NJ (US);

Arthur F Hebard, Bernardsville, NJ (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K / ;
U.S. Cl.
CPC ...
307277 ; 307306 ; 307476 ; 365162 ;
Abstract

Described is a DC powered flip-flop logic or memory element (i.e., circuit) which comprises two Josephson junction gates J.sub.1 and J.sub.2 which operate individually in the latching mode. In one logic state, the gate J.sub.1 is at V.sub.1 =O while J.sub.2 is at V.sub.2 .noteq.O. In the other logic state, the roles of the two junctions are reversed. The two junctions are interconnected by a passive network such that the switching of J.sub.2, say, from V.sub.2 =O to V.sub.2 .noteq.O induces a current-voltage transient on J.sub.1 which returns it to V.sub.1 =O, and conversely.


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