The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 28, 1982

Filed:

Mar. 31, 1980
Applicant:
Inventors:

Mikio Kyomasu, Itami, JP;

Yoshiharu Nakao, Itami, JP;

Mitsuo Nakayama, Itami, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C / ; G11C / ;
U.S. Cl.
CPC ...
365189 ; 365185 ; 365181 ;
Abstract

A memory cell formed of two serially connected MOS transistors one of which has a floating gate is connected to a series combination of a Y address MOS transistor, a readout selection MOS transistor and an MOS transistor disposed in an output buffer circuit across two DC sources. A writing selection MOS transistor is connected across the series combination of the last-mentioned two transistors. The Y address MOS transistor, the readout selection MOS transistor, the output buffer MOS transistor and the writing selection MOS transistor are all operated in the triode region with V.sub.G -V.sub.TH >V.sub.D and at least one of these MOS transistors has a channel conductivity type different from the channel conductivity type of the memory cell MOS transistors.


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