The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 14, 1982
Filed:
Apr. 20, 1979
Masaaki Kusano, Yokohama, JP;
Hitachi, Ltd., Tokyo, JP;
Abstract
In a semiconductor speech path at least a crosspoint element for forming a unitary matrix is formed on a semiconductor chip. The interconnections between the crosspoint elements and the matrix wirings are made on a ceramic wiring plate. By mounting a plurality of semiconductor chips on the ceramic wiring plate by face-down bonding, unitary matrix arrays are formed and at the same time the whole of a matrix array is formed. A row wiring having first speech path wirings and first selection wirings and a column wiring having second speech path wirings and second selection path wirings are doubly layered on the semiconductor wiring plate, with the intervention of an insulating layer therebetween. The upper layer, except for a pedestal region, is covered with a ceramic insulating layer. Terminals for row and column wirings are arranged in dual-in-line fashion. The speech path terminals of each of the row and column wirings are symmetrically and oppositely disposed to each other. This is correspondingly applied for the selection path terminals. With such a construction, the need for the multi-layered wiring on the semiconductor chip is eliminated, and the manufacturing of chips is simplified. Also crosstalk among the row and column wiring paths on the ceramic wiring plate is lessened and the grid wiring is facilitated.