Bell-striking clock

Abstract

An electronic clock emitting half-hourly time signals corresponding to sh' bells comprises an electromagnetic striker driven by a crystal-controlled oscillator via a multistage binary frequency divider whose last several stages, with the exception of the penultimate stage, have outputs interconnected by a logical coincidence gate to generate a succession of output pulses occurring in pairs during the first half of every cycle of a square wave emitted by the final stage. This square wave steps a motor which drives an associated clockwork entraining a multibank rotary switch and alternately closing, for short periods on the full hour and on the half hour, respective contacts which transmit the square wave to a control circuit including an electronic pulse counter. The control circuit, on being triggered by the second half of a wave cycle, emits an enabling signal which unblocks another gate in cascade with the coincidence gate to pass one or more output pulses to the striker for operating same, with simultaneous stepping of the pulse counter which terminates the enabling signal when its count matches a signal code generated by the rotary switch.