The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 26, 1982
Filed:
Aug. 20, 1980
Applicant:
Inventors:
William Rosenbluth, Reston, VA (US);
Thomas A Williams, Reston, VA (US);
Assignee:
IBM Corporation, Armonk, NY (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K / ; H03K / ; H03K / ; G01R / ;
U.S. Cl.
CPC ...
307443 ; 307242 ; 307243 ; 307463 ; 307468 ; 324 / ;
Abstract
A generic FET logic circuit topology is disclosed which employs non-thresholded path routing to eliminate logic transition times in the critical data path. Non-threshold logic performs logic operations with non-inverting unity gain OR and AND functions. The propagation time through the logic matrix is therefore similar to the delay through a chain of linear amplifiers, as contrasted to an algebraic accumulation of delays with conventional logic techniques. This results in an N-factor improvement in the power-delay product over conventional techniques, where N is the number of logic operations being performed.