The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 28, 1982

Filed:

Oct. 20, 1980
Applicant:
Inventor:

Miriam F Young, Dorchester, MA (US);

Assignee:

Honeywell Inc., Minneapolis, MN (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
2957 / ; 29581 ; 29589 ;
Abstract

An improved method of providing a semiconductor device having a semiconductor substrate containing solid state signal processing circuitry. The solid state signal processing circuitry comprises doped regions of predetermined resistivity within the semiconductor substrate. A passivation layer covers a surface of the semiconductor substrate with electrical contacts to the solid state signal processing circuitry exposed through the passivation layer. The improvement comprises forming, on the electrical contacts, contact pads which have an upper surface devoid of a depressed center region. After the forming step, an adhering insulator material is deposited over the passivation layer, and a semiconductor wafer is mounted onto the substrate above the contact pads to form an assembly. The mounting process comprises applying pressure to the assembly and heating the assembly so that, prior to curing, adhering insulator material is squeezed out between the contact pads and a minimum thickness of adhering insulator material remains between the substrate and the wafer. The adhering insulator material is then allowed to cure. Portions of the wafer and adhering insulator material are then removed to expose the upper surface of predetermined contact pads. Predetermined regions of the remaining semiconductor wafer are then electrically interconnected with predetermined contact pads.


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