Frequency sensing circuit

Abstract

A digital circuit for sensing a frequency component F.sub.0 in an applied signal. The amplitude of an input signal is sampled at a clock rate that is N times F.sub.0 and each amplitude sample is encoded as a digital word. The digital words are applied to a first input of an adder, and digital feedback words are applied to a second input of the adder. The output of the adder is applied to a delay circuit which delays the adder output an integral multiple of one-half of the period T.sub.0 corresponding to frequency F.sub.0. The delayed words are multiplied by a constant K whose magnitude is less than one and greater than zero. The delayed and multiplied words are applied as the feedback words to the second input of the adder in phase with the encoded words applied to its first input. A circuit output signal is derived from the adder output, or from the delay circuit output. This circuit output signal has a magnitude indicative of the frequency of the input signal with respect to the clock frequency, and its magnitude is greatest when the input signal frequency is equal to the clock frequency divided by N. The bandwidth of the circuit is adjusted by changing multiplier constant K which is programmable by external signals. Means are provided for adjusting the scale of the digital words applied to the first input of the adder to compensate for changes in K as they occur.