Circuit for correcting phase deviations between the line deflection

Abstract

A substantially digital circuit for correcting phase deviation which comprises a phase comparison stage and a synchronizing control stage. The phase comparison stage includes a reference oscillator, a frequency divider connected to the output of the oscillator and whose output signals constitute the useful line deflection drive signals, as well as a phase comparator comprising a logic circuit and a counter. The logic circuit receives the output signals of the frequency divider and the line synchronizing signals and the counter, which is connected to the output of the oscillator produces a signal which is representative of the phase deviation detected in control stage, the latter comprising a state detector for detecting the synchronized state, in which the phase deviation detected is below a limit value or the unsynchronized state and a correction signal generator for controlling the division ratio of the frequency divider. This frequency divider comprises a counter, an adder, and a decoder the output signal of which is stabilized by means of a stabilizing stage.