Non-volatile random access memory having non-inverted storage

Abstract

A non-volatile random access memory cell has two branches, each branch comprising a source-to-drain channel and a series load connected to the channel to define a node therebetween, each channel having an associated electron tunneling region, a floating gate overlying the channel and a control gate overlying the floating gate, the control gate of each of the branches connected to the node of the other branch and the floating gate of each of the branches overlying the electron tunneling region of the source-to-drain channel of the other branch. The resulting structure is a cross-coupled floating gate structure in which threshold voltage control of one floating gate tunneling metal oxide semiconductor (FATMOS) transistor is controlled by another FATMOS transistor, the two transistors comprising a single random access memory cell. Data may be written in either volatile or non-volatile mode in a state which is not inverted from that previously stored during volatile writing.