The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 07, 1982
Filed:
Mar. 21, 1980
Robert B Jarrett, Tempe, AZ (US);
Wilson D Pace, Tempe, AZ (US);
Motorola, Inc., Schaumburg, IL (US);
Abstract
Structure fabricating using standard integrated injection logic (I.sup.2 L) process techniques for providing a multiple of controlled current source outputs for driving I.sup.2 L to analog interfaces. The current source structure is formed in minimum die area because of the space saving features of I.sup.2 L and tracks the performance of the I.sup.2 L circuit. The current source includes a common P-type emitter region diffused into an isolated N-type epitaxial layer which has been isolated by a deep N+-type diffusion region. Multiple collector P-type regions which are isolated from each other by the N+-type isolating region are diffused into the isolated portion of the epitaxial layer in spaced relationship to the common emitter region. An ion implanted resistor couples the common emitter region to a source of operating potential such that current is injected from the emitter region via the lateral PNP formed transistors to produce multiple output currents from the collector regions. The collector regions are connected using conductive interconnects to respective I.sup.2 L to analog interfaces to provide current for operation of both the open collector I.sup.2 L gates and the analog devices.