Phase locked sampling radio receiver

Abstract

A radio receiver is disclosed in which a received signal is amplified, filtered, and then sampled at a rate determined by a clock signal produced by a selectable-rate, digital oscillator. In sampling the received signal, a family of harmonics are generated which are distributed in a pattern determined by the sampling rate. One harmonic is selected as an intermediate frequency signal and, like the received signal, it is amplified, filtered, and sampled. The second sampling process is driven by a second clock signal produced by a variable-rate, digital oscillator. This produces a second family of harmonics which are derived from the intermediate frequency signal. The second clock signal rate is selected to produce one harmonic which has a carrier component centered on zero frequency. This harmonic, which is the desired baseband signal, is separated from the other harmonics by means of a low-pass filter. The baseband signal is amplified and provided to the user, while at the same time, it is passed through a narrow bandwidth, low-pass filter to extract the carrier component of the signal. The extracted carrier component is digitized to generate a signal that controls the frequency of the variable-rate, digital oscillator. This creates a phase locked loop wherein the variable-rate, digital oscillator generates a clock signal at a rate that maintains the carrier component of the baseband signal centered on zero frequency.