Message-interchange circuitry for microprocessors linked by synchronous

Abstract

A microprocessor associated with a PCM telecommunication network dialogues with remote data-handling components such as other microprocessors through message-interchange circuitry which includes a read/write memory having storage areas individually allocated to several PCM channels, one storage area serving to receive incoming messages destined for the local microprocessor while the remaining storage areas serve for the transmission of outgoing messages intended for respective remote components. A control unit, timed by signals from a synchronization extractor coupled to the network, communicates with the memory to detect state words written by the microprocessor into the memory to indicate the loaded or vacant condition of its storage areas. When the words of an outgoing message are asynchronously written by the local microprocessor into respective cells of a selected transmitting area, a corresponding state word causes the control unit to read out the message words synchronously to the network in the assigned time slot of consecutive PCM frames. Conversely, the words of an incoming message synchronously written into respective cells of the receiving area by the control unit, responding to the arrival of a distinctive start code, are asynchronously read out to the local microprocessor in response to a request signal from the latter.