Self-correcting, solid-state-mass-memory organized by bits and with

Abstract

A mass memory for use with telecommunication equipment comprises a plurality of memory units associated with respective controllers. Each memory unit includes a command module, dialoguing with the associated controller, and a multiplicity of memory modules for the storage of respective information and redundancy bits of a number of data words, one bit of each word being written in an integrated charge-transfer circuit individually assigned thereto and being continuously recirculated when the memory unit is idle. The command module contains a corrective logic which includes a generator of redundancy bits and intervenes during reading and writing phases. An input/output unit, also forming part of the command module, may comprise a switching circuit including a set of multiplexers which may be selectively operated by instructions from the controller to replace a defective memory module by a spare module whose bit-storing circuits already contain the data of the defective module or can receive them in a reinitialization operation. Instead of a single command module, three such modules synchronized with one another can be used to control the reading and writing through majority logic.