The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 27, 1982
Filed:
Jul. 23, 1980
Applicant:
Inventors:
Mitsuo Higuchi, Tokyo, JP;
Kiyoshi Miyasaka, Yokohama, JP;
Assignee:
Fujitsu Limited, Kawasaki, JP;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C / ;
U.S. Cl.
CPC ...
365230 ; 365201 ;
Abstract
An address buffer circuit is used in a memory device, for example in an EPROM device, and enables high speed testing of the memory device. The address buffer circuit can output '1' or '0' from both a positive output terminal and a negative output terminal when an input word address signal having a signal level different from the usual signal level is applied to an input of the address buffer circuit, so that a plurality of word lines can be selected at a time.
Higuchi, Mitsuo. (1982). Address buffer circuit (U.S. Patent No. 4342103). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/4342103
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile