The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 20, 1982

Filed:

May. 17, 1978
Applicant:
Inventors:

Richard E Bakula, Indialantic, FL (US);

Dennis L Maly, Melbourne, FL (US);

James H Weemhoff, Melbourne, FL (US);

Assignee:

Harris Corporation, Cleveland, OH (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F / ;
U.S. Cl.
CPC ...
364200 ;
Abstract

In a unified bus data processing system, a memory expansion unit is connected to the bus to convert bus addresses into addresses in a physical memory which may be many times larger than the maximum size that the bus would have been capable of addressing previously. Thus, the memory expansion unit provides directly addressable memory locations which serve to expand the range of physical addresses allocated to the bus by selectively connecting a plurality of expansion memory units to said bus. The memory expansion unit is programmed to convert groups of bus addresses into the same size group of addresses anywhere in physical memory. Until the memory expansion unit is programmed, physical memory is directly addressable by the central processing unit by applying the appropriate bus address and the normal control signals thereto. The memory expansion unit can also perform a dual mapping function by allocating the expansion memory space differently for the central processor unit than for the other devices connected to the bus. Such control and memory expansion is made available while also retaining the possibility of partial physical memory space on the bus for a portion of the bus address space.


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