Multi-clock data capture circuit

Abstract

A data capture circuit for a logic state analyzer includes a qualifier pattern comparator circuit that responds to a collection of input qualifier signals by producing a number of qualifier pattern signals each representative of the occurrence of a preselectable pattern in the input qualified signals. A like number of clock detection circuits each responds separately to the values of separate clock signals by producing separate qualified clock signals, each of the like number of which represents the simultaneous occurrence of a preselected transition in each particular clock signal and of a qualifier pattern signal associated with that clock signal. The several separate qualified clock signals generally occur at separate times, and each is used to individually capture into several temporary storage registers separate collections of data signal values occurring at those separate times. A master clock selection means allows the user to designate as a master clock signal a qualified clock signal that is expected to occur not earlier in sequence than the others. The master clock signal causes transfer of the contents of the temporary storage registers into intermediate storage registers whose outputs are then merged and combined by subsequent and simultaneous forwarding as a single parallel entity to the main data memory of the logic state analyzer, while at the same time the temporary storage registers are freed to capture fresh data.