The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 15, 1982
Filed:
Sep. 27, 1979
Roger C Palmer, Edmonds, WA (US);
William J Purdue, Edmonds, WA (US);
Interface Mechanisms, Inc., Lynnwood, WA (US);
Abstract
An electrical output signal from an electro-optical code reader is amplified (U1) to develop a first signal which is applied to a positive peak detector (U2D1, C2) and a negative peak detector (U3, D2, C3). The positive peak detector provides a second signal whose voltage level follows that of the first signal as the first signal increases, from the time that the voltage level of the second signal is brought substantially equal to that of the first signal to the time that the first signal begins to decrease, with the voltage level of the second signal thereafter being maintained substantially constant. The negative peak detector provides a third signal whose voltage level follows that of the first signal as the first signal decreases from the time that the voltage level of the third signal is brought substantially equal to that of the first signal to the time that the first signal begins to increase, with the third signal thereafter being maintained substantially constant. The second and third signals are combined (R5,R6) top provide a reference signal whose voltage level is intermediate those of the second and third signals. A comparator (U4) provides a circuit output signal which has a first logic level when the voltage level of the first signal exceeds that of the reference signal and which has a second logic level when the voltage level of the reference signal exceeds that of the first signal. The logic level transitions in the circuit output signal are detected (C4, R10, D6, R11; U5, C5, R9, D7, R 8) to develop pulses which momentarily close fast-acting semiconductor switches (S1, S2) associated with the positive and negative peak detectors, whereby the voltage level of the second signal is brought to that of the first signal at the time that the voltage level of the first signal goes above that of the reference signal, and whereby the voltage level of the third signal is brought to that of the first signal at the time that the voltage level of the first signal goes below that of the reference signal.