Synchronous method and apparatus for speech synthesis circuit

Abstract

A speech synthesis circuit capable of being implemented in an integrated circuit is disclosed. The speech synthesis circuit has an input port for receiving frames of data consisting of speech coefficients, a memory for storing interpolated values of the speech coefficients and an interpolator circuit coupled to the input port and to the memory. A synchronous timing circuit is provided for generating a data frame timing signal, interpolation count timing signals and parameter count timing signals. The rate of the parameter count timing signals is a multiple of the rate of the interpolation count timing signals, which is in turn a multiple of the rate of the data frame timing signal. These signals occur at predetermined times and are generated in the disclosed embodiment by Programmed Logic Arrays (PLA's). The data frame timing signal controls the receipt of a new frame of data at the input port. The interpolation count timing signal controls the initiation of a sequence of interpolations by the interpolator circuit between the values of the speech coefficients of the previous frame of data, and the values of the speech coefficients contained in the current frame. The parameter count timing signals are utilized to control when each coefficient is received at the input port after a data frame timing signal has occurred and also control the transferring of particular speech parameters to the interpolator circuit from the memory.