The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 08, 1982

Filed:

May. 01, 1979
Applicant:
Inventors:

Joel F Boney, Austin, TX (US);

Edward J Rupp, II, Austin, TX (US);

James S Thomas, Manor, TX (US);

Assignee:

Motorola, Inc., Schaumburg, IL (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F / ;
U.S. Cl.
CPC ...
364200 ;
Abstract

A single-chip microcomputer comprises a central processor unit (100), a random access memory (110), a read only memory (120), internal timing circuitry including a timer counter (131), and three I/O data ports (140, 150, and 160). Included within the instruction set of the microcomputer are a branch on bit set instruction and a branch on bit clear instruction. The branch on bit set instruction is a three-byte instruction in which the first byte represents the op code including a designation of a particular bit to be examined, the second byte represents the address of a memory location in which the designated bit is to be examined, and the third byte represents an offset which when combined with the contents of the program counter designates a memory location to which a branch is to be taken if the designated bit is in fact set. For the branch on bit clear instruction, a branch is performed when the particular bit examined is determined not to be set. The branch on bit set and branch on bit clear instructions facilitate serial I/O operations by the microcomputer.


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