The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 25, 1982

Filed:

Mar. 17, 1980
Applicant:
Inventors:

Benedicto U Messina, Poughkeepsie, NY (US);

William D Silkman, Hopewell Junction, NY (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F / ; G06F / ;
U.S. Cl.
CPC ...
364200 ;
Abstract

A fast synonym detection and handling mechanism is disclosed for a cache directory utilizing virtual addressing in data processing systems. The cache directory is divided into 2.sup.N groups of classes, in which N is the number of cache address bits derived from a translatable part of a requested logical address. The cache address is derived from a non-translatable part of the logical address which is used to simultaneously select one class in each of the 2.sup.N groups. The selected class entries are simultaneously compared with one or more dynamic lookaside address translator (DLAT) translated absolute addresses. Compare signals, one for each class entry per DLAT absolute address, are routed to a synonym detection circuit. The detection circuit simultaneously interprets all directory compare signals and determines if a principle hit, synonym hit or a miss occurred in the cache for each request. A principle hit occurs in the group selected by the translatable part of the requested address, and a synonym hit occurs in one of the other groups. If a synonym hit is detected, the group identifier bits for the group having the hit are concatenated with the non-translatable bits used as the cache address for locating the required cache data. For a set-associative cache, set identifier bits are simultaneously generated for cache addressing.


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