The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 04, 1982

Filed:

Sep. 08, 1980
Applicant:
Inventors:

Thorbjoern R Fredriksen, Santa Clara, CA (US);

Philippe Villers, Concord, MA (US);

Assignee:

Computervision Corporation, Bedford, MA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F / ; H04N / ;
U.S. Cl.
CPC ...
364559 ; 356152 ; 356400 ; 358101 ; 364167 ;
Abstract

A method and apparatus for targetless X, Y and .theta. alignment of a semiconductor wafer having thereon a large number of identical microcircuits or dies that are arranged in a pattern to form rows and columns separated by scribe lines or 'streets.' The orientation of the wafer is defined by the location of the wafer flat. Each one of the scribe lines or 'streets' has a known angular relationship with the wafer flat. The alignment method and apparatus utilizes the wafer 'street' pattern for identification instead of special targets located on the wafer. Coarse alignment of the wafer is achieved by locating the wafer flat and then rotating the wafer into approximately correct orientation. Fine alignment of the wafer is performed by opto-electrically locating the edge of a 'street' and then rotating the wafer until the 'street' edge is parallel to either the X or Y principal axis. In the preferred embodiment independent Z-axis compensation is provided to compensate for dimensional surface variations in the wafer.


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