Encoder for recording incremental changes

Abstract

A circuit for detecting leading or lagging phase relationship between first and second two-level input signals at each level transition of both of said input signals and comprising first and second voltage comparators each having first and second input terminals and a single output terminal and each responsive to signals of equal and non-equal logic levels supplied to the first and second input terminals thereof to produce an output signal having high and low logic levels, respectively. First and second input signals are supplied to the first input terminals of the first and second voltage comparators, respectively. A pulse generator responds to each level transition of said first input signal to produce a clock pulse. A decoder responds to the output signals of the first and second voltage comparator to determine the phase relationship of the first and second input signals at each level transition of both input signals and to generate and supply to the second input terminals of the first and second voltage comparators, after each level transition of the second input signal, an acknowledgement signal which prepares the circuit for the reception of the next two level transitions of said input signals.